Resistor Modeling in Verilog-A #verilog #vlsi
1:13
Resistor Modeling in Verilog-A #verilog #vlsi
2 views2 weeks ago
YouTubeCadence Design Systems
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL) [short]
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL) [short]
75 views1 month ago
YouTubeSly Fox electronics
Master the 2:1 Multiplexer! 🔀⚡ | Verilog Code + Testbench + Waveform (Vivado FPGA Tutorial) Review
0:22
Master the 2:1 Multiplexer! 🔀⚡ | Verilog Code + Testbench + Waveform (Vivado FPGA Tutorial) Review
185 views1 week ago
YouTubeSly Fox electronics
conditional statements in verilog | if else & case
2:41
conditional statements in verilog | if else & case
183 views5 months ago
YouTubeChip Logic Studio
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
1:03
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
1.9K views3 months ago
YouTubeCadence Design Systems
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)
633 views5 months ago
YouTubeSly Fox electronics
Digital Versus Analog: Inverter Modeling, Unpacked #vlsi #coding #asicdesign
1:07
Digital Versus Analog: Inverter Modeling, Unpacked #vlsi #coding #asicdesign
635 views1 month ago
YouTubeCadence Design Systems
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
1.5K views4 months ago
YouTubeChip Logic Studio
2:52
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
692 views4 months ago
YouTubeChip Logic Studio
2:51
Verilog Timing Control | Delay Control and Event Synchronization
235 views6 months ago
YouTubeChip Logic Studio
1:24
Difference between Data types of Verilog and SystemVerilog #cadence #chipdesign
1.1K views3 months ago
YouTubeCadence Design Systems
2:34
Finite State Machine (FSM) in Verilog | Code, Testbench & Simulation Explained
116 views3 months ago
YouTubeChip Logic Studio
6:39
Học Ngành Vi Mạch Bán Dẫn: Cơ Hội và Thách Thức
106.9K views11 months ago
TikTokthayquyethuongnghiep
0:54
LÀM CHIP KHÓ LẮM SAO? LỘ TRÌNH 6 BƯỚC ĐỂ TRỞ THÀNH KỸ SƯ THIẾT KẾ IC! ⸻ 1. Thiết kế IC là gì? \t•\tThiết kế IC (Integrated Circuit) là quá trình biến ý tưởng thành vi mạch điện tử. \t•\tGồm 2 mảng chính: \t•\tFront-end: Thiết kế logic – viết code mô tả phần cứng (Verilog/VHDL). \t•\tBack-end: Triển khai layout – thiết kế hình dạng vật lý con chip. ⸻ 2. Lộ trình học chi tiết – Từng bước thực tế: Bước 1: Nắm chắc kiến thức điện tử cơ bản \t•\tMạch điện – điện tử: Op-amp, logic gates, CMOS, MOSFET.
65.2K viewsApr 25, 2025
TikTokongbobitcoin
0:15
FPGA para aplicaciones espaciales
18.2K viewsJun 29, 2025
TikTokcapsula.electronica
0:49
You NEED a complete and up to date LinkedIn profile in 2026. LinkedIn is essentially a search engine for recruiters—if your profile doesn’t have the right keywords, you won’t be found or considered for interviews. To fix this, you need to: 🔑 Target Keywords: Add technical skills like (ex. Python, Verilog, or UVM) to your headline, about section, and experience. 🖼️ Build a Portfolio: Don’t just list skills—post photos of your hardware builds or screen recordings of your code. 📄 Pin Your Resume
4K views6 months ago
TikTokengcalebj28
0:10
Stratosky FPGA - Rumbo a México
3.3K views6 months ago
TikTokcapsula.electronica
0:35
FPGAs Peruanas: Prototipo Oficial y Entrenamiento
10.7K viewsNov 12, 2024
TikTokcapsula.electronica
0:30
Servomotor con FPGA NANO 1k: Proyecto Mecatrónico
6.2K viewsJul 23, 2025
TikTokfpgaedudesign
0:16
Cansados pero felices ,salieron 50 nuevas unidades de placas FPGAs StratoSky para Latam ,gracias Dios por la bendición #verilog #fpgas #systemverilog #Stratosky #vhdl
1.4K views4 months ago
TikTokcapsula.electronica
See more
Static thumbnail place holder